1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, it relates to a semiconductor device including a plurality of interconnection layers and a method of fabricating the same.
2. Description of the Background Art
Following the recently progressed refinement of a semiconductor device, electric resistance has been remarkably increased due to reduction of an interconnection width and the capacitance between adjacent interconnections has been also remarkably increased due to reduction of an interconnection pitch, leading to large interconnection delay. Therefore, it is important to reduce such interconnection delay in the semiconductor device, in order to operate the semiconductor device at a high speed. A delay time resulting from the interconnection delay depends on resistive and capacitive components of the interconnections. In order to reduce the interconnection delay, therefore, it is effective to employ copper (Cu) or the like as the material for the interconnections while employing a material having a low dielectric constant for an insulator film insulating the interconnections from each other thereby reducing the capacitance between the interconnections.
In general, an organic SOG (spin on glass) film, for example, is known as the material having a low dielectric constant employed for the insulator film insulating the interconnections from each other. This organic SOG film is an insulator film mainly composed of silicon dioxide obtained by polymerizing a monomer of a silicon compound containing an organic functional group. When the organic SOG film having a low dielectric constant is employed as the insulator film insulating interconnection layers from each other, the capacitance between the interconnection layers is so reduced as to reduce the interconnection delay.
FIGS. 10 to 12 are sectional views for illustrating a method of fabricating a conventional semiconductor device employing an organic SOG film as an insulator film between interconnection layers. In the method of fabricating the conventional semiconductor device, a plurality of lower interconnections 102 are first formed on an interlayer dielectric film 101 formed on a semiconductor substrate 100 at prescribed intervals, as shown in FIG. 10. A silicon oxide film 103 is formed to cover the interlayer dielectric film 101 and the lower interconnections 102. Thereafter an organic SOG film 104 having a smoothly flattened upper surface is formed on the upper surface of the silicon oxide film 103 by a method of application to fill up the clearances between the lower interconnections 102.
As shown in FIG. 11, a silicon oxide film 106 is deposited on the organic SOG film 104 and the upper surface thereof is polished by CMP (chemical mechanical polishing) to be flattened.
As shown in FIG. 12, contact holes 108 reaching the upper surfaces of some of the lower interconnections 102 are formed through the organic SOG film 104 and the silicon oxide film 106 by ordinary photolithography and anisotropic etching. Metal materials of tungsten (W), copper (Cu) or aluminum (Al) are embedded in the contact holes 108 and the surfaces of the metal materials are flattened by CMP or an etch-back method, thereby forming plugs 109.
In the structure of the conventional semiconductor device shown in FIG. 12, the organic SOG film 104 having a low dielectric constant fills up the clearances between the lower interconnections 102, thereby reducing the capacitance between the adjacent lower interconnections 102.
However, the organic SOG film 104 having low density basically easily absorbs moisture. Further, the organic SOG film 104 has low resistance against plasma. When a resist film (not shown) employed as a mask for forming the contact holes 108 is removed by ashing employing plasma etching, therefore, the organic component forming the organic SOG film 104 is disadvantageously desorbed from the surface portions of the organic SOG film 104 exposed in the contact holes 108. When the organic component is desorbed, the exposed surfaces of the organic SOG film 104 absorb moisture. When the plugs 109 connected to the lower interconnections 102 are formed in the contact holes 108, voids are formed in the plugs 109 by the so-called poisoned via phenomenon due to the moisture discharged from the exposed portions of the organic SOG film 104. The voids formed in the plugs 109 due to the poisoned via phenomenon disadvantageously increase the resistance values of the plugs 109 or cause disconnection.
In order to eliminate the aforementioned inconvenience, there has generally been proposed a technique of implanting ions into an organic SOG film thereby decomposing an organic component contained in the organic SOG film and increasing the density of the organic SOG film, as disclosed in Japanese Patent No. 3015717, Japanese Patent No. 2975934 or Japanese Patent Laying-Open No. 9-312339 (1998), for example. When the organic component is decomposed for increasing the density of the organic SOG film, the organic SOG film is modified.
FIGS. 13 to 16 are sectional views for illustrating a process of fabricating a conventional semiconductor device employing a modified organic SOG film as an insulator film between interconnection layers. In the process of fabricating the conventional semiconductor device, a plurality of lower interconnections 112 are formed on an interlayer dielectric film 111 formed on a semiconductor substrate 110 at prescribed intervals, as shown in FIG. 13. A silicon oxide film 113 is formed to cover the lower interconnections 112 and the interlayer dielectric film 111. An organic SOG film 114 having a flattened upper surface is formed on the silicon oxide film 113 by a method of application to fill up the clearances between the adjacent lower interconnections 112. Thereafter an impurity is ion-implanted into the organic SOG film 114 thereby forming a modified organic SOG film (modified SOG film) 115, as shown in FIG. 14. The density of the modified SOG film 115 is increased by decomposing the organic component through the ion implantation of the impurity.
As shown in FIG. 15, a silicon oxide film 116 is formed on the modified SOG film 115 and the upper surface thereof is thereafter polished by CMP, to be flattened. As shown in FIG. 16, contact holes 118 reaching the upper surfaces of some of the lower interconnections 112 are formed through the silicon oxide film 116 and the modified SOG film 115 by ordinary photolithography and anisotropic etching. Metal materials of W, Cu or Al are embedded in the contact holes 118 and the surfaces thereof are flattened by CMP or an etch-back method, thereby forming plugs 119.
In the structure of the conventional semiconductor device shown in FIG. 16, the modified SOG film 115 increased in density by modifying the organic SOG film 114 is so employed that portions of the modified SOG film 115 hardly absorbing moisture are exposed in the contact holes 118 and inhibited from discharging moisture in formation of the plugs 19. Thus, the plugs 119 can be inhibited from increase of resistance or disconnection in the contact holes 118.
When the modified SOG film 115 is formed by modifying the organic SOG film 114 by ion implantation or the like, however, the dielectric constant intrinsically provided in the organic SOG film 114 is disadvantageously increased. When the modified SOG film 115 is employed as the insulator film between the adjacent lower interconnections 112, the effect of reducing the capacitance between the interconnections is disadvantageously reduced as compared with the case of employing the organic SOG film 104 shown in FIG. 12 as the insulator film between the adjacent lower interconnection 102. Consequently, the effect of reducing interconnection delay is disadvantageously reduced.